Semiconductor Packaging State Of The Art

First, let's explain electronic packaging and how it differs from semiconductor packaging. Electronic packaging involves the design and production of enclosures for electronic devices. This process can be categorized into three main levels, as shown in Figure 1 [1]. As Figure 1 illustrates, the first level pertains to single/multi-chip modules, which are constructed from wafer-based chips. A wafer is a thin, semiconductor round disk that contains hundreds or even thousands of integrated circuits (ICs). The manufacturing process that transforms the wafer into a chip in electronic packaging is known as back-end, or zero-level, packaging. In this article, we delve into this zero-level process and its current status.

Diving deeper into chip manufacturing, we describe how a chip, or in more technical language, a bare die, is produced on a wafer. A bare die is a chip right after it has been cut from the wafer. This chip is termed 'bare' because it lacks any protection from real-world effects such as humidity, dust, and varying temperatures. The production of a bare die on a wafer traditionally involves next steps: Photolithography, Etching, Ion Implantation, Deposition, Chemical Mechanical Planarization, and then packaging. This process can also be seen in Figure 2 [2]. This article will focus only on the last stage of this entire process, the packaging.

The packaging stage exists for several reasons, but one of the most significant is to ensure mechanical and electrical compatibility with the second level of electronic packaging, primarily executed on Printed Circuit Boards (PCB). Initially, packages were made of ceramic and metal, which made them difficult to use due to their high weight. To address this issue, plastic packages were developed, leading to the rapid development of the Dual Inline Package (DIP). DIP features a rectangular body with metal leads extending from two long sides of its plastic body. These leads require through-holes (TH) to be integrated into PCB. This package is still actively used today, but in the 1970s, this package made a revolution in the number of leads that could be used in semiconductor packages, creating the possibility to use more functional chips, such as microcontrollers, that requires more input/output (I/O) leads. The next significant advancement was the development of Surface Mount Devices (SMD), which led to a reduction in PCB costs by 15% and increased PCB density by allowing chips to be installed without TH in the PCB and to be mounted from one side of the PCB only. SMD packaging also led to a high automation rate in PCB manufacturing and component mounting.

In recent years, the push for better technology performance and higher requirements has led to the development of more efficient techniques beyond the traditional wire-bonding and flip-chip, paving the way for advanced semiconductor manufacturing. The term "advanced manufacturing" encompasses all non-traditional methods of chip manufacturing, primarily those that modify some steps from the traditional flow depicted in Figure 2. Advanced manufacturing includes techniques such as Wafer Level Packaging, 2.5D stacking, 3D stacking, among others. These are the primary categories of advanced manufacturing for semiconductor packaging. A more detailed description of these processes will be presented in the following chapters.

In this chapter, we will explore the currently dominant technologies and their dynamics in terms of technical changes over time . We will initially describe the processes, followed by a table that provides a summary and segmentation. Understanding these processes will make the dynamics of innovation in this market more intuitive. Before examining the different processes, it's important to note the main challenges of semiconductor packaging. One of the most significant challenges is heat management. With the increase in density and decrease in the size of the ICs, thermal management has become a critical parameter. Additionally, there are other challenges, such as improving electrical performance while reducing the form factor, addressing cost-reduction challenges, ensuring reliability and longevity, and managing manufacturing complexity.

Processes 

This technology is the most established in the field of semiconductor packaging, utilizing metallic wires to establish connections from the bare die to package pads and the external world, as illustrated in Figure 3 [3]. It claims a significant share of the semiconductor packaging market (20-25%). Wire-bonding is predominantly employed in high-volume production, attributed to the complexity of the manufacturing equipment and the relatively high time and effort required for calibration. The manufacturing process unfolds in the following steps: etching ICs into the wafer, dicing the wafer, placing the bare die onto a wireframe, connecting the two with tiny metallic wires (approximately 18µm in width), and then encapsulating them in plastic or another packaging material.

Although not the newest, this technology maintains a significant presence in the evolving landscape of semiconductor packaging. In contrast to wire bonding, flip-chip technology directly connects the bare die to its package using solder bumps, as illustrated in Figure 4 [4]. This connection method offers lower latency, decreased power consumption, and a reduced size, making it well-suited for applications that demand miniaturization and high performance. Holding a robust market share of 45-50%, flip-chip is applied in various sectors such as mobile telecommunications and high-performance computing. Despite facing challenges like cost, thermal management, and testing, the future looks promising for overcoming these hurdles through advancements in manufacturing and materials. The manufacturing process mirrors that of wire bonding, with the exception of the connection method to the packaging substrate; here, the bare die is faced towards the substrate and linked by solder bumps, as shown in Figure 4.

Although newer than its predecessors, this technique used as base for a whole advanced semiconductor packaging, WLP is significantly impacting the semiconductor packaging industry. The primary distinction of this technology lies in the packaging process being applied to entire wafers before dicing, unlike traditional methods such as wire bonding and flip-chip, which involve dicing the wafer first and then packaging each die individually. The WLP process, as demonstrated in Figure 5 [5], enables a more compact footprint and enhanced efficiency. WLP packages are 30-50% smaller compared to traditional techniques, making them ideal for mobile, wearable, and IoT devices. Furthermore, its scalability and cost-effectiveness hold great promise, with its market share estimated to be between 12-17%. To achieve this advanced performance, encapsulation stage was added into the packaging process, this stage brought packaging of the IC to the wafer so that after dicing the wafer, the chip is already not a bare die but ready to use chip. Despite the challenges of thermal management and increased complexity from further reducing the form factor, WLP continues to advance with innovations like fan-out techniques. These allow for an increased number of input/output (I/O) connections by extending beyond the die boundaries to include redistribution layers (RDL).

2.5D stacking represents a significant advancement in semiconductor packaging, serving as an intermediary between traditional 2D layouts and comprehensive 3D architectures. As shown in Figure 6, [6], this technique involves placing several bare dies on a single interposer (a silicone substrate equipped with high-density routing) before packaging them together to form a unified chip component. This method offers several benefits, including enhanced performance due to shorter inter-chip connections, the capability to integrate a variety of chips (such as logic and memory) within a single package for an integration advantage, and a compact size. Although its market share currently stands at about 5-10%, 2.5D stacking is experiencing rapid growth thanks to its cost-efficiency and manufacturing benefits. Challenges such as thermal management and testing remain. 

1.       This technology enables the vertical integration of chips, optimizing performance and facilitating miniaturization. The possibility of vertical stacking is achieved through the use of Through Silicon Vias (TSV)—extremely small vias that penetrate silicon substrates, like the placement of chips on an interposer in 2.5D stacking. The benefits of this package include minimal connection lengths for lower latency and decreased power consumption, making it ideal for AI and high-performance computing applications. Additionally, its compact size is particularly advantageous for devices requiring extensive miniaturization, such as wearables or augmented reality gadgets. Although currently occupying a niche with a market share of 2.5-6%, 3D stacking is rapidly expanding, driven by improvements in TSV technology. Nevertheless, challenges such as cost, complexity, and thermal management persist. The architecture is depicted in Figure 7 [7].

The above description of the technologies shows that newer, more modern production technologies are available. Most advanced manufacturing technologies have entered the market in the last few decades as can be seen in Figure 8[8], showing a high dynamic in innovative trends. A summary of these technologies is provided in Table 1 below.

Based on various reports, we can identify trends and estimate the market size and its technological segments. Flip-Chip technology claims the largest portion of the market, accounting for approximately 50% of the overall market size. Despite incorporating several optimized techniques, it fundamentally relies on the traditional Flip-Chip process.

Wire-Bonding holds the second-largest market share, distinguished by its enduring presence in the industry with an approximate share of 20%. This dominance is largely due to its cost-effectiveness in the mass production of electronics. The advanced manufacturing sector comprises about 30% of the market, distributed across three primary processes: WLP, 2.5D stacking, and 3D stacking. These techniques are driven by the pursuit of miniaturization and an enhanced performance-footprint ratio.

The semiconductor market was estimated to be worth around $40 billion in 2023, with a Compound Annual Growth Rate (CAGR) of 7-11% based on the referenced reports. As semiconductor packaging forms the foundational layer of electronics packaging, this sector is experiencing a surge in requirements such as reduced form factors and increased performance. These demands are fueling the need for more efficient semiconductor packaging solutions.

According to studies published in the "International Journal of Microwave and Wireless Technologies" and the "International Symposium on Microelectronics,"the semiconductor packaging industry has seen the introduction of new entrants named Additively Manufactured Electronics (AME) technology. Within semiconductor packaging, the AME market presents promising prospects, though it currently represents a niche compared to more established methods. Existing AME implementations mainly target high-performance computing, specialized research, and low-volume production. High-volume packaging's mainstream adoption is still constrained, reflecting the varying capabilities of different AME processes.

AME technologies offer significant advantages, particularly for "on-demand" production. These include facilitating rapid prototyping and the customization of packaging, enabling manufacturers to swiftly introduce new products and meet specific customer demands. Further details on AME benefits are available in a white paper on the J.A.M.E.S. website. Among these advantages, AME promotes increased miniaturization of packaging through highly customized and intricate designs. It supports the integration of various materials into the substrate, offering access to a wide range of included functionalities. This capability allows for heterogeneous integration within packages, potentially enhancing the functionality-footprint ratio, a crucial industry driver.

While AME technologies possess the potential to revolutionize semiconductor packaging, several challenges need addressing. These challenges include ensuring consistent quality and long-term reliability, the establishment of industry-wide standards, achieving cost-competitiveness, and the development of robust software tools. Ongoing innovation in this field, as illustrated in Figure 9, indicates promising developments in quality and reliability. Efforts towards standardization are in progress, strategies for cost reduction are being explored, and software development is tackling current limitations. Overcoming these obstacles and leveraging advancements could significantly impact the packaging industry, moving it towards on-demand customization and enhanced performance. [10]

Research into employing AME processes for connecting bare dies to various substrates has been conducted. This includes evaluating and comparing the performance of AME packaging, primarily against the Wire-Bonded process [9]. AME packages have shown to be competitive with traditional packaging and, in some instances, provide superior performance to wire bonding at frequencies above 20GHz. Given the additional advantage of design customization, AME technology could already complement aspects of Wire-Bonding projects. However, as previously mentioned, other challenges remain that may hinder the broader adoption of AME in final products. The cited research primarily focuses on RF and customization performance, indicating significant effectiveness and potential in RF applications. Nonetheless, overcoming the challenges is essential to achieve a higher Technology Readiness Level (TRL), with the current TRL of AME technology being around 5.

The semiconductor packaging industry stands at a crossroads of huge opportunity and significant challenges. Driven by the key features of miniaturization and performance optimization, this dynamic market witness’s significant growth, with advanced manufacturing techniques like 3D stacking and WLP already capturing a substantial 30% of market share.

However, the horizon holds the potential for even more disruptive shifts. Additively Manufactured Electronics (AME) emerges as a promising new player, offering the intriguing potential for highly customized, on-demand production with increasing resolution. While still in its infancy, AME technology makes relatively rapid advancements, raising excitement within the industry.

Challenges, however, persist. Ensuring consistent quality, reliability, and cost-effectiveness remains paramount for AME's widespread adoption. Standardization across materials, processes, and design is crucial to overcome. Overcoming these obstacles will unlock the full potential of AME, potentially revolutionizing the industry towards agile, customized, and high-performance packaging solutions.

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